The host processor updates the GRAM only when the image changes (e.g., a static UI or a notification update). Once written, the DSI link drops into an ultra-low power sleep state while the display panel refreshes itself locally.
In Video Mode, the host processor must continuously stream real-time pixel data to the display, mimicking traditional RGB or LVDS interfaces. mipi dsi specification pdf
employs differential signaling for video data, supporting per-lane data rates of up to 1.5 Gbps (in the original D-PHY specification). A 4-lane configuration is mandatory for 4K+ resolutions, with each lane supporting 1.5 Gbps in High-Speed mode. The host processor updates the GRAM only when
When selecting an interface for a new product, it is essential to understand where DSI fits in. mipi dsi specification pdf