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| Week | Topic | Key Concepts | Reading | Assignment | |------|-------|--------------|---------|-------------| | 1 | Performance Fundamentals | Latency, throughput, CPI, Amdahl’s law, SPEC benchmarks | P&H Ch.1 | Worksheet: Performance equations | | 2 | ISA Design | RISC-V / MIPS ISA, addressing modes, encoding, RISC vs. CISC | P&H Ch.2 | ISA comparison essay | | 3 | Single-cycle & Multi-cycle Datapath | ALU, register file, control logic, clock cycles | P&H Ch.4 | Verilog datapath simulation | | 4 | Pipelining I | 5-stage pipeline, structural/data hazards, forwarding | P&H Ch.4.5-4.7 | Pipeline hazard detection (C++) | | 5 | Pipelining II | Control hazards, branch prediction (static/dynamic), BTB | P&H Ch.4.8 | Branch predictor simulator | | 6 | Memory Hierarchy I | Cache organization (direct, set-associative), write policies | P&H Ch.5.1-5.3 | Cache trace analysis (Python) | | 7 | Midterm Exam | Weeks 1-6 | - | Proctored exam | | 8 | Memory Hierarchy II | DRAM timing, prefetching, TLB, virtual memory | P&H Ch.5.4-5.7 | gem5 cache config experiment | | 9 | Out-of-Order Execution | Scoreboarding, Tomasulo’s algorithm, ROB | H&H Ch.7 | Tomasulo simulation (Java/Python) | | 10 | Advanced ILP | Superscalar, VLIW, speculative execution, register renaming | H&H Ch.7.6-7.9 | Speculative execution write-up | | 11 | SIMD & Vector Processors | Vector lanes, gather/scatter, GPU basics | P&H App.G | Vectorization exercise (AVX) | | 12 | Multiprocessors I | Shared memory, cache coherence (MSI/MESI), snooping | P&H Ch.5.8-5.10 | Coherence protocol FSM design | | 13 | Multiprocessors II | Directory-based coherence, memory consistency models (SC, TSO, RC) | P&H Ch.5.11-5.13 | Consistency litmus test analysis | | 14 | Final Project & Review | Project presentations, future trends (near-memory computing, CXL) | Selected papers | Final report & peer review | | Week | Topic | Key Concepts |